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|Title:||Si-nanowire based gate-all-around nonvolatile SONOS memory cell||Authors:||Fu, J.
Nonvolatile memory (NVM)
|Issue Date:||May-2008||Citation:||Fu, J., Singh, N., Buddharaju, K.D., Teo, S.H.G., Shen, C., Jiang, Y., Zhu, C.X., Yu, M.B., Lo, G.Q., Balasubramanian, N., Kwong, D.L., Gnani, E., Baccarani, G. (2008-05). Si-nanowire based gate-all-around nonvolatile SONOS memory cell. IEEE Electron Device Letters 29 (5) : 518-521. ScholarBank@NUS Repository. https://doi.org/10.1109/LED.2008.920267||Abstract:||This letter presents a high-speed silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory cell in gateall-around Si-nanowire (NW) architecture, which is fabricated by using a top-down process technology. The NW cell exhibits faster program and erase (P/E) speed compared to the corresponding planar device; 1 μs for programming and 1 ms for erasing at VGS = ±11 V with a threshold voltage shift "ΔVTH" of 2.6 V using the Fowler-Nordheim tunneling mechanism. At these P/E conditions, the planar device does not show appreciable change. The improvement is originated from: 1) increased electric field at the Si-SiO2 interface; 2) reduced effective tunnel barrier width; and 3) low electric field in the blocking oxide, as analyzed through simulation. In addition, good data retention makes the NW-based SONOS cell a potential candidate for future high-speed low-voltage NAND-type nonvolatile Flash memory applications. © 2008 IEEE.||Source Title:||IEEE Electron Device Letters||URI:||http://scholarbank.nus.edu.sg/handle/10635/83028||ISSN:||07413106||DOI:||10.1109/LED.2008.920267|
|Appears in Collections:||Staff Publications|
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