Characterization and reliability of dual high-k gate dielectric stack (poly-Si-HfO2-SiO2) prepared by in situ RTCVD process for system-on-chip applications

Abstract

We investigate for the first time the possibility of integrating chemical vapor deposition (CVD) HfO2 into the multiple gate dielectric system-on-a-chlp (SoC) process in the range of 6-7 nm, which supports higher voltage (2.5-5-V operation/tolerance). Results show that CVD HfO2-SiO2 stacked gate dielectric (EOT = 6.2 nm) exhibits lower leakage current than that of SiO2 (EOT = 5.7 nm) by a factor of ∼102, with comparable interface quality (Dit ∼ 1 × 1010 cm-2 eV-1). The presence of negative fixed charge is observed in HfO2-SiO2 gate stack. In addition, the addition of HfO2 on SiO2 does not alter the dominant conduction mechanism of Fowler-Nordheim tunneling in HfO2-SiO2 gate stack. Furthermore, the HfO2-SiO2 gate stack shows longer time to breakdown TBD than SiO2 under constant voltage stress. These results suggest that it may be feasible to use such a gate stack for higher voltage operation in SoC, provided other key requirements such as Vt stability (charge trapping under stress) can be met and the negative fixed charge eliminated.