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https://doi.org/10.1109/LED.2013.2244056
| Title: | A junctionless gate-all-around silicon nanowire FET of high linearity and its potential applications | Authors: | Wang, T. Lou, L. Lee, C. |
Keywords: | linearity silicon nanowire (SiNW) FET Third-order intermodulation (IM3) |
Issue Date: | 2013 | Citation: | Wang, T., Lou, L., Lee, C. (2013). A junctionless gate-all-around silicon nanowire FET of high linearity and its potential applications. IEEE Electron Device Letters 34 (4) : 478-480. ScholarBank@NUS Repository. https://doi.org/10.1109/LED.2013.2244056 | Abstract: | The linearity of a gate-all-around junctionless silicon nanowire (SiNW) FET has been analyzed. The SiNW FET shows a perfectly linear ID-V G relation and a nearly zero output conductance. The mechanism of its linear behaviors due to degenerate doping level has been also demonstrated. For RF applications, the proposed SiNW FET exhibits a much lower distortion for a whole range of load resistance, making it superior to modern short-channel MOSFET. © 1980-2012 IEEE. | Source Title: | IEEE Electron Device Letters | URI: | http://scholarbank.nus.edu.sg/handle/10635/81879 | ISSN: | 07413106 | DOI: | 10.1109/LED.2013.2244056 |
| Appears in Collections: | Staff Publications |
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