Please use this identifier to cite or link to this item: https://doi.org/10.1109/LED.2013.2244056
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dc.titleA junctionless gate-all-around silicon nanowire FET of high linearity and its potential applications
dc.contributor.authorWang, T.
dc.contributor.authorLou, L.
dc.contributor.authorLee, C.
dc.date.accessioned2014-10-07T04:22:47Z
dc.date.available2014-10-07T04:22:47Z
dc.date.issued2013
dc.identifier.citationWang, T., Lou, L., Lee, C. (2013). A junctionless gate-all-around silicon nanowire FET of high linearity and its potential applications. IEEE Electron Device Letters 34 (4) : 478-480. ScholarBank@NUS Repository. https://doi.org/10.1109/LED.2013.2244056
dc.identifier.issn07413106
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/81879
dc.description.abstractThe linearity of a gate-all-around junctionless silicon nanowire (SiNW) FET has been analyzed. The SiNW FET shows a perfectly linear ID-V G relation and a nearly zero output conductance. The mechanism of its linear behaviors due to degenerate doping level has been also demonstrated. For RF applications, the proposed SiNW FET exhibits a much lower distortion for a whole range of load resistance, making it superior to modern short-channel MOSFET. © 1980-2012 IEEE.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/LED.2013.2244056
dc.sourceScopus
dc.subjectlinearity
dc.subjectsilicon nanowire (SiNW) FET
dc.subjectThird-order intermodulation (IM3)
dc.typeArticle
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.doi10.1109/LED.2013.2244056
dc.description.sourcetitleIEEE Electron Device Letters
dc.description.volume34
dc.description.issue4
dc.description.page478-480
dc.description.codenEDLED
dc.identifier.isiut000316813100001
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