Please use this identifier to cite or link to this item:
https://doi.org/10.1109/LED.2013.2244056
DC Field | Value | |
---|---|---|
dc.title | A junctionless gate-all-around silicon nanowire FET of high linearity and its potential applications | |
dc.contributor.author | Wang, T. | |
dc.contributor.author | Lou, L. | |
dc.contributor.author | Lee, C. | |
dc.date.accessioned | 2014-10-07T04:22:47Z | |
dc.date.available | 2014-10-07T04:22:47Z | |
dc.date.issued | 2013 | |
dc.identifier.citation | Wang, T., Lou, L., Lee, C. (2013). A junctionless gate-all-around silicon nanowire FET of high linearity and its potential applications. IEEE Electron Device Letters 34 (4) : 478-480. ScholarBank@NUS Repository. https://doi.org/10.1109/LED.2013.2244056 | |
dc.identifier.issn | 07413106 | |
dc.identifier.uri | http://scholarbank.nus.edu.sg/handle/10635/81879 | |
dc.description.abstract | The linearity of a gate-all-around junctionless silicon nanowire (SiNW) FET has been analyzed. The SiNW FET shows a perfectly linear ID-V G relation and a nearly zero output conductance. The mechanism of its linear behaviors due to degenerate doping level has been also demonstrated. For RF applications, the proposed SiNW FET exhibits a much lower distortion for a whole range of load resistance, making it superior to modern short-channel MOSFET. © 1980-2012 IEEE. | |
dc.description.uri | http://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/LED.2013.2244056 | |
dc.source | Scopus | |
dc.subject | linearity | |
dc.subject | silicon nanowire (SiNW) FET | |
dc.subject | Third-order intermodulation (IM3) | |
dc.type | Article | |
dc.contributor.department | ELECTRICAL & COMPUTER ENGINEERING | |
dc.description.doi | 10.1109/LED.2013.2244056 | |
dc.description.sourcetitle | IEEE Electron Device Letters | |
dc.description.volume | 34 | |
dc.description.issue | 4 | |
dc.description.page | 478-480 | |
dc.description.coden | EDLED | |
dc.identifier.isiut | 000316813100001 | |
Appears in Collections: | Staff Publications |
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