Construct GaAs FET dc model from drain-port dc power and conductance

Abstract

This paper presents an empirical approach to construct the nonlinear dc model of FET. The dc power consumption Pd (Ids×Vds) and the dc output conductance Gd (Ids/Vds) are fitted first. Then the drain current is derived by square rooting the multiply of the dc power and dc conductance. This approach makes it easier to find the nonlinear functions used in the model and gives more flexibility in choosing the number of fitting parameters than conventional methods. A FET dc model has been developed through this approach and gives good agreement between simulation and measured Ids and gm. Its accuracy in predicating the drain source current, transconductance, drain-source conductance is compared with other models.