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|Title:||Automatic IC Die Positioning in the SEM||Authors:||Tan, H.W.
|Issue Date:||2000||Citation:||Tan, H.W.,Phang, J.C.H.,Thong, J.T.L. (2000). Automatic IC Die Positioning in the SEM. Conference Proceedings from the International Symposium for Testing and Failure Analysis : 469-477. ScholarBank@NUS Repository.||Abstract:||This paper presents a new automatic die positioning system for failure analysis work in the scanning electron microscope (SEM). The system makes use of machine vision to automatically locate a prespecified failure site on an integrated circuit (IC) sample, without the need for a high-accuracy specimen stage or modifications to existing SEM hardware. Depending on the appearance of the desired failure site, either image registration or feature tracking is used to locate the site. To locate failure sites containing unique and distinguishing features, such as those found on logic ICs, an image registration procedure is used. Experiments carried out on a microprocessor and an analogue-to-digital converter show that the new system is able to accurately locate the failure site, even in the presence of IC sample rotation and image scaling. Moreover, the accuracy of the technique has been shown to be independent of the complexity and minimum feature size of the sample used. To locate failure sites containing repetitive IC patterns, such as those from DRAM samples, a feature tracking approach was incorporated into the original die positioning algorithm. The final system can therefore locate many types of failure sites, regardless of whether they have unique features or repetitive IC patterns.||Source Title:||Conference Proceedings from the International Symposium for Testing and Failure Analysis||URI:||http://scholarbank.nus.edu.sg/handle/10635/72500|
|Appears in Collections:||Staff Publications|
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