Warpage Detection during Baking of Semiconductor substrate in Microlithography

Abstract

Wafer warpage is common in microelectronics processing. Warped wafers can affect device performance, reliability and linewidth control in various processing steps. We proposed in this paper an in-situ fault detection technique for wafer warpage in microlithography. Early detection will minimize cost and processing time. Based on first principle thermal modeling, we are able to detect warpage fault from available temperature measurements. Experimental results demonstrate the feasibility of the approach. The proposed approach is applicable to other semiconductor substrates.