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|Title:||Tighter WCET analysis of input dependent programs with classified-cache memory architecture||Authors:||Yanhui, L.
|Issue Date:||2008||Citation:||Yanhui, L.,Fernando, S.D.,Heng, Y.,Xiaolei, C.,Yajun, H.,Teng, T.T. (2008). Tighter WCET analysis of input dependent programs with classified-cache memory architecture. Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008 : 410-413. ScholarBank@NUS Repository. https://doi.org/10.1109/ICECS.2008.4674877||Abstract:||Caches in Embedded Systems improve average case performance, but they are a source of unpredictability, especially in the worst case software timing analysis with the consideration of data caches. This is a critical problem in real-time systems, where tight Worst Case Execution Time (WCET) is required for their schedulability analysis. Several works have studied the data cache impacts on the WCET of programs, but they can only handle programs with no input dependent data accesses. To solve this problem, we have developed a novel architecture and a WCET analysis framework for this architecture. Our work classifies predictable and unpredictable accesses and allocates them into predictable caches and unpredictable caches respectively, using the CME (Cache Miss Equations) and reuse-distance based algorithms accordingly. The analysis framework produces a very good WCET tightness compared with simulations, and our architecture creates almost no hardware overhead or performance degradation. © 2008 IEEE.||Source Title:||Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008||URI:||http://scholarbank.nus.edu.sg/handle/10635/72024||ISBN:||9781424421824||DOI:||10.1109/ICECS.2008.4674877|
|Appears in Collections:||Staff Publications|
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