Performance breakthrough in 8 nm gate length gate-all-around nanowire transistors using metallic nanowire contacts

Please use this identifier to cite or link to this item: https://doi.org/10.1109/VLSIT.2008.4588553

Title:	Performance breakthrough in 8 nm gate length gate-all-around nanowire transistors using metallic nanowire contacts
Authors:	Jiang, Y. Liow, T.Y. Singh, N. Tan, L.H. Lo, G.Q. Chan, D.S.H. Kwong, D.L.
Issue Date:	2008
Citation:	Jiang, Y.,Liow, T.Y.,Singh, N.,Tan, L.H.,Lo, G.Q.,Chan, D.S.H.,Kwong, D.L. (2008). Performance breakthrough in 8 nm gate length gate-all-around nanowire transistors using metallic nanowire contacts. Digest of Technical Papers - Symposium on VLSI Technology : 34-35. ScholarBank@NUS Repository. https://doi.org/10.1109/VLSIT.2008.4588553
Abstract:	Parasitic S/D resistances in extremely scaled GAA nanowire devices can pathologically limit the device drive current performance. We demonstrate for the first time, that S/D extension dopant profile engineering together with successful integration of low resistivity metallic nanowire contacts greatly reduces parasitic resistances. This allows 8nm gate length GAA nanowire devices in this work to attain record-high drive currents of 3740μA/μm. © 2008 IEEE.
Source Title:	Digest of Technical Papers - Symposium on VLSI Technology
URI:	http://scholarbank.nus.edu.sg/handle/10635/71399
ISBN:	9781424418053
ISSN:	07431562
DOI:	10.1109/VLSIT.2008.4588553
Appears in Collections:	Staff Publications

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