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https://doi.org/10.1109/ICSICT.2008.4734778
| Title: | Interface engineering for high-k/Ge gate stack | Authors: | Xie, R. Zhu, C. |
Issue Date: | 2008 | Citation: | Xie, R.,Zhu, C. (2008). Interface engineering for high-k/Ge gate stack. International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT : 1252-1255. ScholarBank@NUS Repository. https://doi.org/10.1109/ICSICT.2008.4734778 | Abstract: | In this paper, various interface engineering techniques for high-k/Ge gate stack for advanced CMOS device applications are reviewed. High-k gate stack formation on Ge substrate is first addressed with emphasis on pre-gate surface passivation. Post gate dielectric (post-gate) treatments are then discussed to further improve the high-k/Ge interface quality. © 2008 IEEE. | Source Title: | International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT | URI: | http://scholarbank.nus.edu.sg/handle/10635/70647 | ISBN: | 9781424421855 | DOI: | 10.1109/ICSICT.2008.4734778 |
| Appears in Collections: | Staff Publications |
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