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Please use this identifier to cite or link to this item: https://doi.org/10.1109/ICSICT.2008.4734778
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dc.titleInterface engineering for high-k/Ge gate stack
dc.contributor.authorXie, R.
dc.contributor.authorZhu, C.
dc.date.accessioned2014-06-19T03:14:33Z
dc.date.available2014-06-19T03:14:33Z
dc.date.issued2008
dc.identifier.citationXie, R.,Zhu, C. (2008). Interface engineering for high-k/Ge gate stack. International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT : 1252-1255. ScholarBank@NUS Repository. <a href="https://doi.org/10.1109/ICSICT.2008.4734778" target="_blank">https://doi.org/10.1109/ICSICT.2008.4734778</a>
dc.identifier.isbn9781424421855
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/70647
dc.description.abstractIn this paper, various interface engineering techniques for high-k/Ge gate stack for advanced CMOS device applications are reviewed. High-k gate stack formation on Ge substrate is first addressed with emphasis on pre-gate surface passivation. Post gate dielectric (post-gate) treatments are then discussed to further improve the high-k/Ge interface quality. © 2008 IEEE.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/ICSICT.2008.4734778
dc.sourceScopus
dc.typeConference Paper
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.doi10.1109/ICSICT.2008.4734778
dc.description.sourcetitleInternational Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT
dc.description.page1252-1255
dc.identifier.isiutNOT_IN_WOS
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