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|Title:||An automatic mapping from Statecharts to Verilog||Authors:||Tran, V.-A.V.
|Issue Date:||2005||Citation:||Tran, V.-A.V.,Qin, S.,Chin, W.N. (2005). An automatic mapping from Statecharts to Verilog. Lecture Notes in Computer Science 3407 : 187-203. ScholarBank@NUS Repository.||Abstract:||Statecharts is a visual formalism suitable for high-level system specification, while Verilog is a hardware description language that can be used for both behavioural and structural specification of (hardware) systems. This paper implements a semantics-preserving mapping from Graphical Statecharts to Verilog programs, which, to the best of our knowledge, is the first algorithm to bridge the gap between Statecharts and Verilog, and can be embedded into the hardware/software co-specification process  as a front-end. © Springer-Verlag Berlin Heidelberg 2005.||Source Title:||Lecture Notes in Computer Science||URI:||http://scholarbank.nus.edu.sg/handle/10635/43326||ISSN:||03029743|
|Appears in Collections:||Staff Publications|
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