Please use this identifier to cite or link to this item: https://scholarbank.nus.edu.sg/handle/10635/43326
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dc.titleAn automatic mapping from Statecharts to Verilog
dc.contributor.authorTran, V.-A.V.
dc.contributor.authorQin, S.
dc.contributor.authorChin, W.N.
dc.date.accessioned2013-07-23T09:31:03Z
dc.date.available2013-07-23T09:31:03Z
dc.date.issued2005
dc.identifier.citationTran, V.-A.V.,Qin, S.,Chin, W.N. (2005). An automatic mapping from Statecharts to Verilog. Lecture Notes in Computer Science 3407 : 187-203. ScholarBank@NUS Repository.
dc.identifier.issn03029743
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/43326
dc.description.abstractStatecharts is a visual formalism suitable for high-level system specification, while Verilog is a hardware description language that can be used for both behavioural and structural specification of (hardware) systems. This paper implements a semantics-preserving mapping from Graphical Statecharts to Verilog programs, which, to the best of our knowledge, is the first algorithm to bridge the gap between Statecharts and Verilog, and can be embedded into the hardware/software co-specification process [19] as a front-end. © Springer-Verlag Berlin Heidelberg 2005.
dc.sourceScopus
dc.typeConference Paper
dc.contributor.departmentSINGAPORE-MIT ALLIANCE
dc.contributor.departmentCOMPUTER SCIENCE
dc.description.sourcetitleLecture Notes in Computer Science
dc.description.volume3407
dc.description.page187-203
dc.identifier.isiutNOT_IN_WOS
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