Please use this identifier to cite or link to this item: https://doi.org/10.1038/s41467-021-26230-x
Title: Wafer-scale functional circuits based on two dimensional semiconductors with fabrication optimized by machine learning
Authors: Chen, Xinyu
Xie, Yufeng
Sheng, Yaochen
Tang, Hongwei
Wang, Zeming
Wang, Yu
Wang, Yin
Liao, Fuyou
Ma, Jingyi
Guo, Xiaojiao
Tong, Ling
Liu, Hanqi
Liu, Hao
Wu, Tianxiang
Cao, Jiaxin
Bu, Sitong
Shen, Hui
Bai, Fuyu
Huang, Daming
Deng, Jianan
Riaud, Antoine
Xu, Zihan
Wu, Chenjian
Xing, Shiwei
Lu, Ye
Ma, Shunli
Sun, Zhengzong
Xue, Zhongyin
Di, Zengfeng
Gong, Xiao 
Zhang, David Wei
Zhou, Peng
Wan, Jing
Bao, Wenzhong
Issue Date: 12-Oct-2021
Publisher: Nature Research
Citation: Chen, Xinyu, Xie, Yufeng, Sheng, Yaochen, Tang, Hongwei, Wang, Zeming, Wang, Yu, Wang, Yin, Liao, Fuyou, Ma, Jingyi, Guo, Xiaojiao, Tong, Ling, Liu, Hanqi, Liu, Hao, Wu, Tianxiang, Cao, Jiaxin, Bu, Sitong, Shen, Hui, Bai, Fuyu, Huang, Daming, Deng, Jianan, Riaud, Antoine, Xu, Zihan, Wu, Chenjian, Xing, Shiwei, Lu, Ye, Ma, Shunli, Sun, Zhengzong, Xue, Zhongyin, Di, Zengfeng, Gong, Xiao, Zhang, David Wei, Zhou, Peng, Wan, Jing, Bao, Wenzhong (2021-10-12). Wafer-scale functional circuits based on two dimensional semiconductors with fabrication optimized by machine learning. Nature Communications 12 (1) : 5953. ScholarBank@NUS Repository. https://doi.org/10.1038/s41467-021-26230-x
Rights: Attribution 4.0 International
Abstract: Triggered by the pioneering research on graphene, the family of two-dimensional layered materials (2DLMs) has been investigated for more than a decade, and appealing functionalities have been demonstrated. However, there are still challenges inhibiting high-quality growth and circuit-level integration, and results from previous studies are still far from complying with industrial standards. Here, we overcome these challenges by utilizing machine-learning (ML) algorithms to evaluate key process parameters that impact the electrical characteristics of MoS2 top-gated field-effect transistors (FETs). The wafer-scale fabrication processes are then guided by ML combined with grid searching to co-optimize device performance, including mobility, threshold voltage and subthreshold swing. A 62-level SPICE modeling was implemented for MoS2 FETs and further used to construct functional digital, analog, and photodetection circuits. Finally, we present wafer-scale test FET arrays and a 4-bit full adder employing industry-standard design flows and processes. Taken together, these results experimentally validate the application potential of ML-assisted fabrication optimization for beyond-silicon electronic materials. © 2021, The Author(s).
Source Title: Nature Communications
URI: https://scholarbank.nus.edu.sg/handle/10635/231909
ISSN: 2041-1723
DOI: 10.1038/s41467-021-26230-x
Rights: Attribution 4.0 International
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