Please use this identifier to cite or link to this item: https://doi.org/10.1038/s41467-021-26230-x
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dc.titleWafer-scale functional circuits based on two dimensional semiconductors with fabrication optimized by machine learning
dc.contributor.authorChen, Xinyu
dc.contributor.authorXie, Yufeng
dc.contributor.authorSheng, Yaochen
dc.contributor.authorTang, Hongwei
dc.contributor.authorWang, Zeming
dc.contributor.authorWang, Yu
dc.contributor.authorWang, Yin
dc.contributor.authorLiao, Fuyou
dc.contributor.authorMa, Jingyi
dc.contributor.authorGuo, Xiaojiao
dc.contributor.authorTong, Ling
dc.contributor.authorLiu, Hanqi
dc.contributor.authorLiu, Hao
dc.contributor.authorWu, Tianxiang
dc.contributor.authorCao, Jiaxin
dc.contributor.authorBu, Sitong
dc.contributor.authorShen, Hui
dc.contributor.authorBai, Fuyu
dc.contributor.authorHuang, Daming
dc.contributor.authorDeng, Jianan
dc.contributor.authorRiaud, Antoine
dc.contributor.authorXu, Zihan
dc.contributor.authorWu, Chenjian
dc.contributor.authorXing, Shiwei
dc.contributor.authorLu, Ye
dc.contributor.authorMa, Shunli
dc.contributor.authorSun, Zhengzong
dc.contributor.authorXue, Zhongyin
dc.contributor.authorDi, Zengfeng
dc.contributor.authorGong, Xiao
dc.contributor.authorZhang, David Wei
dc.contributor.authorZhou, Peng
dc.contributor.authorWan, Jing
dc.contributor.authorBao, Wenzhong
dc.date.accessioned2022-10-11T07:45:46Z
dc.date.available2022-10-11T07:45:46Z
dc.date.issued2021-10-12
dc.identifier.citationChen, Xinyu, Xie, Yufeng, Sheng, Yaochen, Tang, Hongwei, Wang, Zeming, Wang, Yu, Wang, Yin, Liao, Fuyou, Ma, Jingyi, Guo, Xiaojiao, Tong, Ling, Liu, Hanqi, Liu, Hao, Wu, Tianxiang, Cao, Jiaxin, Bu, Sitong, Shen, Hui, Bai, Fuyu, Huang, Daming, Deng, Jianan, Riaud, Antoine, Xu, Zihan, Wu, Chenjian, Xing, Shiwei, Lu, Ye, Ma, Shunli, Sun, Zhengzong, Xue, Zhongyin, Di, Zengfeng, Gong, Xiao, Zhang, David Wei, Zhou, Peng, Wan, Jing, Bao, Wenzhong (2021-10-12). Wafer-scale functional circuits based on two dimensional semiconductors with fabrication optimized by machine learning. Nature Communications 12 (1) : 5953. ScholarBank@NUS Repository. https://doi.org/10.1038/s41467-021-26230-x
dc.identifier.issn2041-1723
dc.identifier.urihttps://scholarbank.nus.edu.sg/handle/10635/231909
dc.description.abstractTriggered by the pioneering research on graphene, the family of two-dimensional layered materials (2DLMs) has been investigated for more than a decade, and appealing functionalities have been demonstrated. However, there are still challenges inhibiting high-quality growth and circuit-level integration, and results from previous studies are still far from complying with industrial standards. Here, we overcome these challenges by utilizing machine-learning (ML) algorithms to evaluate key process parameters that impact the electrical characteristics of MoS2 top-gated field-effect transistors (FETs). The wafer-scale fabrication processes are then guided by ML combined with grid searching to co-optimize device performance, including mobility, threshold voltage and subthreshold swing. A 62-level SPICE modeling was implemented for MoS2 FETs and further used to construct functional digital, analog, and photodetection circuits. Finally, we present wafer-scale test FET arrays and a 4-bit full adder employing industry-standard design flows and processes. Taken together, these results experimentally validate the application potential of ML-assisted fabrication optimization for beyond-silicon electronic materials. © 2021, The Author(s).
dc.publisherNature Research
dc.rightsAttribution 4.0 International
dc.rights.urihttps://creativecommons.org/licenses/by/4.0/
dc.sourceScopus OA2021
dc.typeArticle
dc.contributor.departmentELECTRICAL AND COMPUTER ENGINEERING
dc.description.doi10.1038/s41467-021-26230-x
dc.description.sourcetitleNature Communications
dc.description.volume12
dc.description.issue1
dc.description.page5953
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