Please use this identifier to cite or link to this item: https://doi.org/10.1063/1.5058717
Title: In0.49Ga0.51P/GaAs heterojunction bipolar transistors (HBTs) on 200 mm Si substrates: Effects of base thickness, base and sub-collector doping concentrations
Authors: Wang, Y
Lee, K.H
Loke, W.K 
Ben Chiah, S
Zhou, X
Yoon, S.F 
Tan, C.S
Fitzgerald, E
Keywords: Buffer layers
Gallium arsenide
Heterojunctions
III-V semiconductors
Metallorganic chemical vapor deposition
Power amplifiers
Semiconductor doping
Silicon wafers
Substrates
Telephone sets
Collector doping
DC current gain
Doping concentration
Germaniums (Ge)
Heterojunction bipolar transistor (HBTs)
Mobile phone handsets
Monolithic integration
Silicon substrates
Heterojunction bipolar transistors
Issue Date: 2018
Citation: Wang, Y, Lee, K.H, Loke, W.K, Ben Chiah, S, Zhou, X, Yoon, S.F, Tan, C.S, Fitzgerald, E (2018). In0.49Ga0.51P/GaAs heterojunction bipolar transistors (HBTs) on 200 mm Si substrates: Effects of base thickness, base and sub-collector doping concentrations. AIP Advances 8 (11) : 115132. ScholarBank@NUS Repository. https://doi.org/10.1063/1.5058717
Rights: Attribution 4.0 International
Abstract: We report performance of InGaP/GaAs heterojunction bipolar transistors (HBTs) fabricated on epitaxial films directly grown onto 200 mm silicon (Si) substrates using a thin 100% germanium (Ge) buffer layer. Both buffer layer and device layers were grown epitaxially using metalorganic chemical vapor deposition (MOCVD). With the assistance of numerical simulation, we were able to achieve high performance GaAs HBTs with DC current gain of ?100 through optimizing the base doping concentration (C-doped, ? 1.9×1019/cm3), base layer thickness (?55 nm), and the sub-collector doping concentration (Te-doped, > 5×1018/cm3). The breakdown voltage at base (BVceo) of higher than 9.43 V was realized with variation of < 3% across the 200 mm wafer. These results could enable applications such as power amplifiers for mobile phone handsets and monolithic integration of HBTs with standard Si-CMOS transistors on a common Si platform. © 2018 Author(s).
Source Title: AIP Advances
URI: https://scholarbank.nus.edu.sg/handle/10635/182070
ISSN: 21583226
DOI: 10.1063/1.5058717
Rights: Attribution 4.0 International
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