Please use this identifier to cite or link to this item: https://doi.org/10.1109/TVLSI.2013.2239671
Title: Failure Mitigation Techniques for 1T-1MTJ Spin-Transfer Torque MRAM Bit-cells
Authors: Fong, Xuanyao 
Kim, Yusung
Choday, Sri Harsha
Roy, Kaushik
Keywords: Science & Technology
Technology
Computer Science, Hardware & Architecture
Engineering, Electrical & Electronic
Computer Science
Engineering
Bit-cell optimization
failure mitigation
magnetic tunneling junction (MTJ)
spin-transfer torque magnetic RAM (STT-MRAM)
MAGNETIC TUNNEL-JUNCTIONS
STT-MRAM
Issue Date: 1-Feb-2014
Publisher: IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Citation: Fong, Xuanyao, Kim, Yusung, Choday, Sri Harsha, Roy, Kaushik (2014-02-01). Failure Mitigation Techniques for 1T-1MTJ Spin-Transfer Torque MRAM Bit-cells. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 22 (2) : 384-395. ScholarBank@NUS Repository. https://doi.org/10.1109/TVLSI.2013.2239671
Abstract: The emergence of spin-transfer torque magnetic RAM (STT-MRAM) as a leading candidate for future high-performance nonvolatile memory has led to increased research interest. Current STT-MRAM technology faces several major obstacles in attaining its potential. One of the major issues is in the design of 1T-1MTJ STT-MRAM bit-cells under process variations: the bit-cells need to be significantly upsized to improve bit-cell failure, resulting in increased bit-cell area and power dissipation. In this paper, we analyze four circuit-level solutions that enable smaller 1T-1MTJ STT-MRAM bit-cells with improved yield, namely, bit-line voltage boosting, word-line voltage boosting, access transistor body biasing, and an applied external magnetic field. Results from simulation using 45-nm bulk CMOS access transistor and 40-nm magnetic tunneling junction technology show that word-line voltage boosting can be the best failure mitigation technique. Bit-cells designed with word-line boosting for write has a bit-cell area reduced by > 75% at iso-failure probability, compared to bit-cells without any failure mitigation technique. When bit-cell failure probability is optimized instead, 5 Oe of applied external magnetic field assisted write reduces power consumption by > 15%, compared to bit-cells designed without failure mitigation techniques. © 1993-2012 IEEE.
Source Title: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
URI: https://scholarbank.nus.edu.sg/handle/10635/156174
ISSN: 1063-8210
1557-9999
DOI: 10.1109/TVLSI.2013.2239671
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