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Pey Kin Leong

rp03121

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Full Name
Pey Kin Leong
Variants
PEY, KIN-LEONG
PEY, KIN L.
LEONG, KIN
Pey, Kin Leong
PEY, KIN LEONG
Pey, K.L.
 
Main Affiliation
 
Faculty
 

Publications

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Type:  Patent
Department:  ELECTRICAL & COMPUTER ENGINEERING

Results 1-7 of 7 (Search time: 0.003 seconds).

Issue DateTitleAuthor(s)
120-May-2003Incorporation of dielectric layer onto SThM tips for direct thermal analysisHU, CHANG CHAUN; PEY, KIN LEONG ; CHONG, YUNG FU; KIN, CHIM WAI ; NEUZIL, PAVEL; CHAN, LAP
224-Jan-2012Method for fabricating semiconductor devices with shallow diffusion regionsTAN, DEXTER XUEMING; COLOMBEAU, BENJAMIN; ONG, CLARK KUANG KIAN; YEONG, SAI HOOI; NG, CHEE MANG ; PEY, KIN LEONG 
315-Feb-2011Method for forming a shallow junction region using defect engineering and laser annealingONG, KUANG KIAN; YEONG, SAI HOOI; PEY, KIN LEONG ; CHAN, LAP; CHONG, YUNG FU
430-Jan-2001Method to fabricate a double-polysilicon gate structure for a sub-quarter micron self-aligned-titanium silicide processPEY, KIN-LEONG ; HO, CHAW SING; CHAN, LAP
51-Jan-2002Method to form MOS transistors with shallow junctions using laser annealingCHONG, YUNG FU; PEY, KIN LEONG ; SEE, ALEX ; WEE, ANDREW THYE SHEN 
64-Sep-2001Method to reduce compressive stress in the silicon substrate during silicidationCHA, RANDALL CHER LIANG; CHUA, CHEE TEE; PEY, KIN LEONG ; CHAN, LAP
725-Jul-2000Ultra-low sheet resistance metal/poly-si gate for deep sub-micron CMOS applicationLIM, CHONG WEE; PEY, KIN LEONG ; SIAH, SOH YUN; LIM, ENG HWA ; CHAN, LAP