Please use this identifier to cite or link to this item: https://doi.org/10.1109/TED.2013.2271643
DC FieldValue
dc.titlePhase change liner stressor for strain engineering of P-channel FinFETs
dc.contributor.authorDing, Y.
dc.contributor.authorCheng, R.
dc.contributor.authorKoh, S.-M.
dc.contributor.authorLiu, B.
dc.contributor.authorYeo, Y.-C.
dc.date.accessioned2014-10-07T04:34:38Z
dc.date.available2014-10-07T04:34:38Z
dc.date.issued2013
dc.identifier.citationDing, Y., Cheng, R., Koh, S.-M., Liu, B., Yeo, Y.-C. (2013). Phase change liner stressor for strain engineering of P-channel FinFETs. IEEE Transactions on Electron Devices 60 (9) : 2703-2711. ScholarBank@NUS Repository. https://doi.org/10.1109/TED.2013.2271643
dc.identifier.issn00189383
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/82884
dc.description.abstractA novel Ge2Sb2Te5 (GST) liner stressor for enhancing the drive current in p-channel FinFETs (p-FinFETs) is demonstrated. When amorphous GST changes phase to crystalline GST (c-GST), the GST material contracts. This phenomenon is exploited for strain engineering of p-FinFETs. A GST liner stressor wrapping a p-FinFET can be shrunk or contracted to generate very high channel stress for drive current enhancement. Saturation drain current enhancement of ~80% and linear drain current enhancement of ~110% are observed for FinFETs with c-GST liner stressor over the control or unstrained FinFETs. The drain current enhancement is higher for 0° rotated FinFETs as compared with that of the FinFETs with 45° rotation, due to the orientation-dependent piezoresistance coefficients. The drain current enhancement increases with decreasing gate length. GST liner stressor could be a strain engineering option in sub-20-nm technology nodes. © 1963-2012 IEEE.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/TED.2013.2271643
dc.sourceScopus
dc.subjectFinFET
dc.subjectGe2Sb2Te5 (GST)
dc.subjectMultigate FET
dc.subjectPhase change
dc.subjectStrai
dc.typeArticle
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.doi10.1109/TED.2013.2271643
dc.description.sourcetitleIEEE Transactions on Electron Devices
dc.description.volume60
dc.description.issue9
dc.description.page2703-2711
dc.description.codenIETDA
dc.identifier.isiut000323640300001
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