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|Title:||Leakage suppression of gated diodes fabricated under low-temperature annealing with substitutional carbon Si1-yCy incorporation||Authors:||Tan, C.F.
Solid-phase epitaxy re-growth (SPER)
|Issue Date:||Apr-2005||Citation:||Tan, C.F.,Chor, E.F.,Lee, H.,Liu, J.,Quek, E.,Chan, L. (2005-04). Leakage suppression of gated diodes fabricated under low-temperature annealing with substitutional carbon Si1-yCy incorporation. IEEE Electron Device Letters 26 (4) : 252-254. ScholarBank@NUS Repository. https://doi.org/10.1109/LED.2005.845501||Abstract:||We have demonstrated the fabrication of n+-p gated diodes using low-temperature annealing of 700 °C for 30 s with a significantly reduced junction leakage current, This is achieved with the incorporation of an epitaxially grown Si1-yC(y = 0.0007) layer in the substrate located at the end-of-range (EOR) of arsenic implantations. The carbon devices show effectively suppressed EOR defects in the cross-sectional transmission electron microscopy images and leakage characteristics similar to the controlled silicon device fabricated under high-temperature annealing of 950 °C for 30 s. Arrhenius measurement of the leakage profiles has indicated identical leakage mechanism for both the pure silicon and carbon devices, thus signifying the substantial elimination of the secondary EOR defects resulted from the implantations despite the low-temperature annealing of the latter. © 2005 IEEE.||Source Title:||IEEE Electron Device Letters||URI:||http://scholarbank.nus.edu.sg/handle/10635/82616||ISSN:||07413106||DOI:||10.1109/LED.2005.845501|
|Appears in Collections:||Staff Publications|
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