Tackling the drop impact reliability of electronic packaging

Abstract

A 3-year collaboration program between the Institute of Microelectronics, National University of Singapore, and the University of Cambridge has been established with the following two objectives: (i) to establish a mechanics and physics-of-failure based board-level test methodology; (ii) to establish design guidelines and, ultimately, failure criteria for board level interconnect during drop/impact test. The following accomplishments have been achieved in the first year of the program: (i) the mechanics and physics of failure in a typical board-level test have been established (ii) the drop impact characteristics of 6 commercial portable products have been comprehensively surveyed; (iii) a weakness has been identified in the drop impact strength of SnAgCu solder alloy (acknowledged as the leading Pb-free solder candidate).