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|Title:||Device performance-based OPC for optimal circuit performance and mask cost reduction||Authors:||Teh, S.-H.
|Keywords:||Design for manufacturability (DFM)
|Issue Date:||2008||Citation:||Teh, S.-H., Heng, C.-H., Tay, A. (2008). Device performance-based OPC for optimal circuit performance and mask cost reduction. Proceedings of SPIE - The International Society for Optical Engineering 6925 : -. ScholarBank@NUS Repository. https://doi.org/10.1117/12.772285||Abstract:||During the Design-to-Manufacturing tape out flow, Optical Proximity Correction (OPC) is commonly adopted to correct the systematic proximity-effects-caused patterning distortions in order to minimize the across-gate and across-chip linewidth variation. With the continued scaling of gate length, the OPC correction scheme inevitably becomes more aggressive nowadays; increasing the mask complexity and cost proportionally. This could partly be attributed to the purely geometry-based OPC algorithm which tries to match every edge in the layout, without considering its actual impact on circuit performance. Therefore, possibility exists for over-corrected OPC mask that bring slight improvement in circuit performance at the expense of disproportionate higher cost. To simplify the mask design, we present a device performance-based OPC (DPB-OPC) algorithm to generate the mask based on the performance matching criteria rather than the geometrical pattern matching criteria. Drive current (Ion) and leakage current (Ioff) of transistor are chosen to be the performance indexes in this DPB-OPC flow. When compared to the conventional OPC approaches, our proposed approach results in simpler mask that achieves closer circuit performance.||Source Title:||Proceedings of SPIE - The International Society for Optical Engineering||URI:||http://scholarbank.nus.edu.sg/handle/10635/69932||ISBN:||9780819471109||ISSN:||0277786X||DOI:||10.1117/12.772285|
|Appears in Collections:||Staff Publications|
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