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|Title:||ASIP-controlled inverse integer transform for H.264/AVC compression||Authors:||Ngo, N.T.
|Issue Date:||2008||Citation:||Ngo, N.T., Do, T.T.T., Le, T.M., Kadam, Y.S., Bermak, A. (2008). ASIP-controlled inverse integer transform for H.264/AVC compression. Proceedings The 19th IEEE/IFIP International Symposium on Rapid System Prototyping - Shortening the Path from Specification to Prototype, RSP 2008 : 158-164. ScholarBank@NUS Repository. https://doi.org/10.1109/RSP.2008.34||Abstract:||In this paper, an Application-Specific Instruction Set Processor (ASIP) -controlled inverse integer transform IP block on a System-on-Chip (SoC) platform is proposed. The proposed design is implemented as an independently operated IP block connected to the ASIP via the Wishbone SoC bus. It features both 4×4 and 8×8 inverse integer transform with additional support for 2×2 and 4×4 Hadamard transforms of DC coefficients. Design portability can be achieved by using the open Wishbone standard for the system bus with a moderate increase in system area. The IP block is controlled by an ASIP which allows functional testability and design flexibility. Compared with existing designs in its class, the circuit area of this design is considerably minimal due to the embodiment of 4×4 circuit in the 8×8 circuit, while achieving a speed of 176MHz. © 2008 IEEE. DOI 10.1109/RSP.2008.34.||Source Title:||Proceedings The 19th IEEE/IFIP International Symposium on Rapid System Prototyping - Shortening the Path from Specification to Prototype, RSP 2008||URI:||http://scholarbank.nus.edu.sg/handle/10635/69451||ISBN:||9780769531809||DOI:||10.1109/RSP.2008.34|
|Appears in Collections:||Staff Publications|
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