ASIP-controlled inverse integer transform for H.264/AVC compression

Abstract

In this paper, an Application-Specific Instruction Set Processor (ASIP) -controlled inverse integer transform IP block on a System-on-Chip (SoC) platform is proposed. The proposed design is implemented as an independently operated IP block connected to the ASIP via the Wishbone SoC bus. It features both 4×4 and 8×8 inverse integer transform with additional support for 2×2 and 4×4 Hadamard transforms of DC coefficients. Design portability can be achieved by using the open Wishbone standard for the system bus with a moderate increase in system area. The IP block is controlled by an ASIP which allows functional testability and design flexibility. Compared with existing designs in its class, the circuit area of this design is considerably minimal due to the embodiment of 4×4 circuit in the 8×8 circuit, while achieving a speed of 176MHz. © 2008 IEEE. DOI 10.1109/RSP.2008.34.