A Gigahertz Wideband CMOS multiplier for UWB Transceiver

Please use this identifier to cite or link to this item: https://doi.org/10.1109/ISCAS.2005.1465778

Title:	A Gigahertz Wideband CMOS multiplier for UWB Transceiver
Authors:	Zhou, L. Xu, Y.P. Lin, F.
Issue Date:	2005
Citation:	Zhou, L.,Xu, Y.P.,Lin, F. (2005). A Gigahertz Wideband CMOS multiplier for UWB Transceiver. Proceedings - IEEE International Symposium on Circuits and Systems : 5087-5090. ScholarBank@NUS Repository. https://doi.org/10.1109/ISCAS.2005.1465778
Abstract:	A wideband CMOS differential four-quadrant analog multiplier is described. The multiplier is designed to implement a correlator for Ultra Wideband (UWB) transceivers. With the dominant pole at the internal node being cancelled, the bandwidth of the multiplier can be increased as much as five times under no load condition. The simulation shows that the bandwidths of the multiplier can be as high as 10GHz without the load and 7GHz when loaded by an output buffer. The multiplier is able to operate with a 0.2-ns narrow monocycle pulse. The multiplier is based on a 0.18-um CMOS process and operates under a 1.8-V supply. © 2008 IEEE.
Source Title:	Proceedings - IEEE International Symposium on Circuits and Systems
URI:	http://scholarbank.nus.edu.sg/handle/10635/68824
ISSN:	02714310
DOI:	10.1109/ISCAS.2005.1465778
Appears in Collections:	Staff Publications

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