Please use this identifier to cite or link to this item: https://doi.org/10.1109/ISCAS.2005.1465778
DC FieldValue
dc.titleA Gigahertz Wideband CMOS multiplier for UWB Transceiver
dc.contributor.authorZhou, L.
dc.contributor.authorXu, Y.P.
dc.contributor.authorLin, F.
dc.date.accessioned2014-06-19T02:53:38Z
dc.date.available2014-06-19T02:53:38Z
dc.date.issued2005
dc.identifier.citationZhou, L.,Xu, Y.P.,Lin, F. (2005). A Gigahertz Wideband CMOS multiplier for UWB Transceiver. Proceedings - IEEE International Symposium on Circuits and Systems : 5087-5090. ScholarBank@NUS Repository. <a href="https://doi.org/10.1109/ISCAS.2005.1465778" target="_blank">https://doi.org/10.1109/ISCAS.2005.1465778</a>
dc.identifier.issn02714310
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/68824
dc.description.abstractA wideband CMOS differential four-quadrant analog multiplier is described. The multiplier is designed to implement a correlator for Ultra Wideband (UWB) transceivers. With the dominant pole at the internal node being cancelled, the bandwidth of the multiplier can be increased as much as five times under no load condition. The simulation shows that the bandwidths of the multiplier can be as high as 10GHz without the load and 7GHz when loaded by an output buffer. The multiplier is able to operate with a 0.2-ns narrow monocycle pulse. The multiplier is based on a 0.18-um CMOS process and operates under a 1.8-V supply. © 2008 IEEE.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/ISCAS.2005.1465778
dc.sourceScopus
dc.typeConference Paper
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.doi10.1109/ISCAS.2005.1465778
dc.description.sourcetitleProceedings - IEEE International Symposium on Circuits and Systems
dc.description.page5087-5090
dc.description.codenPICSD
dc.identifier.isiutNOT_IN_WOS
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