NEW PIPELINED VECTOR-REDUCTION ARITHMETIC UNIT FOR FIR FILTER IMPLEMENTATION.

Abstract

In realizing an N-tap finite impulse-response (FIR) filter, N multiplications and N-1 additions must be performed during every sampling interval. The multiplication process can be pipelined easily because there is no recurrence. The (N-1)-port addition process is essentially a vector-reduction process with inherent recurrence and is a bottleneck of hardware utilization when implemented using a pipelined arithmetic unit. We present a new pipeline structure of implementing the multiport adder. For an arithmetic pipeline with M segments, our new design achieves the theoretical upper bound on hardware utilization provided that N greater than equivalent to (L plus 2)M minus 2**L** plus **1 where L equals Int (log//2(M)), the largest integer less than or equal to log**2(M). This pipeline structure is also useful in pipelined signal-processor design.