Please use this identifier to cite or link to this item:
https://scholarbank.nus.edu.sg/handle/10635/62480
DC Field | Value | |
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dc.title | NEW PIPELINED VECTOR-REDUCTION ARITHMETIC UNIT FOR FIR FILTER IMPLEMENTATION. | |
dc.contributor.author | Lim, Y.C. | |
dc.date.accessioned | 2014-06-17T06:51:29Z | |
dc.date.available | 2014-06-17T06:51:29Z | |
dc.date.issued | 1987-07 | |
dc.identifier.citation | Lim, Y.C. (1987-07). NEW PIPELINED VECTOR-REDUCTION ARITHMETIC UNIT FOR FIR FILTER IMPLEMENTATION.. IEE Proceedings E: Computers and Digital Techniques 134 (4) : 189-196. ScholarBank@NUS Repository. | |
dc.identifier.issn | 01437062 | |
dc.identifier.uri | http://scholarbank.nus.edu.sg/handle/10635/62480 | |
dc.description.abstract | In realizing an N-tap finite impulse-response (FIR) filter, N multiplications and N-1 additions must be performed during every sampling interval. The multiplication process can be pipelined easily because there is no recurrence. The (N-1)-port addition process is essentially a vector-reduction process with inherent recurrence and is a bottleneck of hardware utilization when implemented using a pipelined arithmetic unit. We present a new pipeline structure of implementing the multiport adder. For an arithmetic pipeline with M segments, our new design achieves the theoretical upper bound on hardware utilization provided that N greater than equivalent to (L plus 2)M minus 2**L** plus **1 where L equals Int (log//2(M)), the largest integer less than or equal to log**2(M). This pipeline structure is also useful in pipelined signal-processor design. | |
dc.source | Scopus | |
dc.type | Article | |
dc.contributor.department | ELECTRICAL ENGINEERING | |
dc.description.sourcetitle | IEE Proceedings E: Computers and Digital Techniques | |
dc.description.volume | 134 | |
dc.description.issue | 4 | |
dc.description.page | 189-196 | |
dc.description.coden | IPETD | |
dc.identifier.isiut | NOT_IN_WOS | |
Appears in Collections: | Staff Publications |
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