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|Title:||A pipelined hardware implementation of In-loop Deblocking Filter in H.264/AVC||Authors:||Khurana, G.
In-loop Deblocking Filter
|Issue Date:||May-2006||Citation:||Khurana, G., Kassim, A.A., Chua, T.P., Mi, M.B. (2006-05). A pipelined hardware implementation of In-loop Deblocking Filter in H.264/AVC. IEEE Transactions on Consumer Electronics 52 (2) : 536-540. ScholarBank@NUS Repository. https://doi.org/10.1109/TCE.2006.1649676||Abstract:||In this paper we present a pipelined hardware implementation of In-loop Deblocking Filter in H.264/AVC. A pipelined datapath has been adopted to boost the speed of the deblocking filter process. The processing order of the filter is rearranged to facilitate the deblocking of the pixels in a pipelined fashion. A suitable buffer mechanism has also been proposed that reduces the size of the on-chip SRAM and redundant external memory accesses. The hardware implementation, under TSMC 0.13 μm standard cell library, consumes only 7.5 K gates at a clock frequency of 200MHz. Our architecture supports real-time deblocking of high resolution (2048×1024) video applications at 30 fps over three channels. © 2006 IEEE.||Source Title:||IEEE Transactions on Consumer Electronics||URI:||http://scholarbank.nus.edu.sg/handle/10635/54712||ISSN:||00983063||DOI:||10.1109/TCE.2006.1649676|
|Appears in Collections:||Staff Publications|
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