A fast in situ approach to estimating wafer warpage profile during thermal processing in microlithography

Abstract

Wafer warpage can affect device performance, reliability and linewidth control in various processing steps in microelectronics manufacturing. Early detection will minimize cost and processing time. We have previously demonstrated an on-line approach for detecting wafer warpage and the profile of the warped wafer. The proposed approach demonstrates that the profile of the wafer can be computed during thermal processing steps in the lithography sequence. However, the approach is computationally intensive and information is made available at the end of the thermal processing step. Any attempts at real-time correction of the wafer temperature are thus not possible. In this paper, we proposed an in situ approach to detect wafer warpage and its profile midway through the thermal process. Based on first principles thermal modelling, we are able to detect and estimate the profile of a warped wafer from available temperature measurements. The proposed approach can be implemented on conventional thermal processing systems. Experimental results demonstrate the feasibility and repeatability of the approach. A 75% improvement in computational time is achieved with the proposed approach. © 2006 IOP Publishing Ltd.