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|Title:||A DSP-based video compression test-bed||Authors:||Kassim, A.A.
|Issue Date:||May-1997||Citation:||Kassim, A.A.,Fong, F.K.,Chua, K.S.,Rangananth, S. (1997-05). A DSP-based video compression test-bed. Microprocessors and Microsystems 20 (9) : 541-551. ScholarBank@NUS Repository.||Abstract:||This paper presents a DSP-based video compression system that was developed to serve as a platform for the testing and implementation of different video compression algorithms. The system consists of three main functional units; the video encoder, the video decoder and the audio codec processor. Each functional unit consists of a Texas Instruments TMS320C30 digital signal processor. A complete implementation of the H.261 video communications standard on the system is also presented. © 1997 Elsevier Science B.V.||Source Title:||Microprocessors and Microsystems||URI:||http://scholarbank.nus.edu.sg/handle/10635/54094||ISSN:||01419331|
|Appears in Collections:||Staff Publications|
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