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Please use this identifier to cite or link to this item: https://scholarbank.nus.edu.sg/handle/10635/54094
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dc.titleA DSP-based video compression test-bed
dc.contributor.authorKassim, A.A.
dc.contributor.authorFong, F.K.
dc.contributor.authorChua, K.S.
dc.contributor.authorRangananth, S.
dc.date.accessioned2014-06-16T09:26:57Z
dc.date.available2014-06-16T09:26:57Z
dc.date.issued1997-05
dc.identifier.citationKassim, A.A.,Fong, F.K.,Chua, K.S.,Rangananth, S. (1997-05). A DSP-based video compression test-bed. Microprocessors and Microsystems 20 (9) : 541-551. ScholarBank@NUS Repository.
dc.identifier.issn01419331
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/54094
dc.description.abstractThis paper presents a DSP-based video compression system that was developed to serve as a platform for the testing and implementation of different video compression algorithms. The system consists of three main functional units; the video encoder, the video decoder and the audio codec processor. Each functional unit consists of a Texas Instruments TMS320C30 digital signal processor. A complete implementation of the H.261 video communications standard on the system is also presented. © 1997 Elsevier Science B.V.
dc.sourceScopus
dc.subjectH.261 standard
dc.subjectTMS320C30
dc.subjectVideo compression
dc.typeArticle
dc.contributor.departmentELECTRICAL ENGINEERING
dc.description.sourcetitleMicroprocessors and Microsystems
dc.description.volume20
dc.description.issue9
dc.description.page541-551
dc.description.codenMIMID
dc.identifier.isiutNOT_IN_WOS
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