Imporved algorithms for low power multiplexor decomposition

Abstract

It has been estimated that multiplexors (MUXes) make up a major portion of the circuitry in a typical chip. Therefore, to reduce power consumption of a chip, it is important to consider the problem of low power design of MUXes. This problem is called the low power MUX decomposition problem and has been studied in [3]. This paper improves on the result of [3] in two ways: (a) we propose a method to speed-up the algorithms in [3] (by factors of up to 7.1 for 64-to-1 MUXes), and (b) we propose a post optimization procedure to further reduce the overall power dissipation of the decomposition obtained by [3] or any other MUX decomposition algorithms. Using this procedure, we have been able to further reduce the power dissipation results of [3].