Strained Multiple - Gate Transistors With Si/SiC and Si/SiGe Heterojunctions

Abstract

High performance multiple-gate transistors such as FinFETs are likely to be required beyond the 32 nm technology node. Process-induced strain techniques can significantly enhance the carrier mobility in the channels of such transistors. In this dissertation work, complementary lattice mismatched source and drain stressors are studied for both n and p-channel multiple-gate transistors. Si1-yCy (or SiC), which has a lattice constant smaller than that of Si, is employed to induce uniaxial tensile strain in the channel regions of n-channel devices. Si1-xGex (or SiGe), which has a lattice constant larger than that of Si, is employed to induce uniaxial compressive strain in the channel regions of p-channel devices.