Please use this identifier to cite or link to this item: https://scholarbank.nus.edu.sg/handle/10635/28155
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dc.titleStrained Multiple - Gate Transistors With Si/SiC and Si/SiGe Heterojunctions
dc.contributor.authorLIOW TSUNG-YANG
dc.date.accessioned2011-11-08T18:00:56Z
dc.date.available2011-11-08T18:00:56Z
dc.date.issued2008-09-30
dc.identifier.citationLIOW TSUNG-YANG (2008-09-30). Strained Multiple - Gate Transistors With Si/SiC and Si/SiGe Heterojunctions. ScholarBank@NUS Repository.
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/28155
dc.description.abstractHigh performance multiple-gate transistors such as FinFETs are likely to be required beyond the 32 nm technology node. Process-induced strain techniques can significantly enhance the carrier mobility in the channels of such transistors. In this dissertation work, complementary lattice mismatched source and drain stressors are studied for both n and p-channel multiple-gate transistors. Si1-yCy (or SiC), which has a lattice constant smaller than that of Si, is employed to induce uniaxial tensile strain in the channel regions of n-channel devices. Si1-xGex (or SiGe), which has a lattice constant larger than that of Si, is employed to induce uniaxial compressive strain in the channel regions of p-channel devices.
dc.language.isoen
dc.subjectstrain, finfet, mugfet, silicon-germanium, silicon-carbon
dc.typeThesis
dc.contributor.departmentNUS GRAD SCH FOR INTEGRATIVE SCI & ENGG
dc.description.degreePh.D
dc.description.degreeconferredDOCTOR OF PHILOSOPHY
dc.identifier.isiutNOT_IN_WOS
Appears in Collections:Ph.D Theses (Open)

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