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Title: Standard Cell-Based Ultra-Compact DACs in 40-nm CMOS
Authors: Aiello, O. 
Crovetti, P.
Alioto, M. 
Keywords: Automated design
Digital to analog converter (DAC)
Fully digital
Fully synthesizable
Standard-cell-based analog circuits
Ultra-low design effort
Issue Date: 2019
Publisher: Institute of Electrical and Electronics Engineers Inc.
Citation: Aiello, O., Crovetti, P., Alioto, M. (2019). Standard Cell-Based Ultra-Compact DACs in 40-nm CMOS. IEEE Access 7 : 126479-126488. ScholarBank@NUS Repository.
Rights: Attribution-NonCommercial-NoDerivatives 4.0 International
Abstract: In this paper, very compact, standard cell-based Digital-to-Analog converters (DACs) based on the Dyadic Digital Pulse Modulation (DDPM) are presented. As fundamental contribution, an optimal sampling condition is analytically derived to enhance DDPM conversion with inherent suppression of spurious harmonics. Operation under such optimal condition is experimentally demonstrated to assure resolution up to 16 bits, with 9.4-239X area reduction compared to prior art. The digital nature of the circuits also allows extremely low design effort in the order of 10 man-hours, portability across CMOS generations, and operation at the lowest supply voltage reported to date. The limitations of DDPM converters, the benefits of the optimal sampling condition and digital calibration were explored through the optimized design and the experimental characterization of two DACs with moderate and high resolution. The first is a general-purpose DAC for baseband signals achieving 12-bit (11.6 ENOB) resolution at 110kS/s sample rate and consuming 50.8? W, the second is a DAC for DC calibration achieving 16-bit resolution with 3.1-LSB INL, 2.5-LSB DNL, 45? W power, at only 530? m2 area. © 2013 IEEE.
Source Title: IEEE Access
ISSN: 2169-3536
DOI: 10.1109/ACCESS.2019.2938737
Rights: Attribution-NonCommercial-NoDerivatives 4.0 International
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