Please use this identifier to cite or link to this item: https://scholarbank.nus.edu.sg/handle/10635/192143
Title: Trimming-Less 0.2-V, 3.2-pW Voltage Reference Based on Corner-Aware Replica Combination with 1.6% Process Sensitivity, 1.4-mV Accuracy across PVT and Wafers
Authors: Fassio, Luigi 
De Rose, Raffaele
Longyang Lin 
Lanuzza, Marco
Crupi, Felice
Alioto, Massimo Bruno 
Issue Date: 2-Jun-2021
Publisher: IEEE
Citation: Fassio, Luigi, De Rose, Raffaele, Longyang Lin, Lanuzza, Marco, Crupi, Felice, Alioto, Massimo Bruno (2021-06-02). Trimming-Less 0.2-V, 3.2-pW Voltage Reference Based on Corner-Aware Replica Combination with 1.6% Process Sensitivity, 1.4-mV Accuracy across PVT and Wafers. IEEE ESSCIRC 2021. ScholarBank@NUS Repository.
Abstract: This work introduces a class of voltage references able to operate down to 3.2 pW and 0.2-V supply for energy harvesting with relaxed or suppressed voltage regulation (direct harvesting). Inherent wafer-to-wafer process sensitivity limitations and effect of process corners in deep sub-threshold are mitigated via a selection/combination of circuit replicas driven by a process sensor, at zero testing effort and trimming. A 180-nm testchip shows 1.6% process sensitivity (including wafer-to-wafer variations), 60.7-µV/V line sensitivity, and 34.9-µV/oC temperature coefficient, leading to 1.4-mV overall accuracy across corner wafers.
Source Title: IEEE ESSCIRC 2021
URI: https://scholarbank.nus.edu.sg/handle/10635/192143
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