Please use this identifier to cite or link to this item: https://doi.org/10.1109/LSSC.2020.3025191
Title: Fully-Synthesizable All-Digital Unified Dynamic Entropy Generation, Extraction and Utilization within the Same Cryptographic Core
Authors: SACHIN TANEJA 
ALIOTO,MASSIMO BRUNO 
Keywords: Hardware security
TRNGs
dynamic entropy
private key cryptography
pulsed latch
constrained secure systems
Issue Date: 18-Sep-2020
Publisher: Institute of Electrical and Electronics Engineers Inc.
Citation: SACHIN TANEJA, ALIOTO,MASSIMO BRUNO (2020-09-18). Fully-Synthesizable All-Digital Unified Dynamic Entropy Generation, Extraction and Utilization within the Same Cryptographic Core. IEEE Solid-State Circuits Letters 3 : 402 - 405. ScholarBank@NUS Repository. https://doi.org/10.1109/LSSC.2020.3025191
Rights: CC0 1.0 Universal
Abstract: This work introduces a novel class of fully-synthesizable all-digital True Random Number Generators (TRNGs) using the same private-key cryptographic core for raw dynamic entropy generation, its extraction via post-processing, and its utilization as crypto-key for constrained secure systems. Endogenous random bit generation is achieved via clock pulsewidth overstretching in the digital implementation of private-key cryptographic algorithms using pulsed-latch pipelines, leveraging inherent Shannon confusion and diffusion. Demonstration on a 40-nm testchip based on a SIMON cryptographic core shows 64-bit key encryption down to 0.25 pJ/bit at 0.45 V, random number generation with cryptographic-grade entropy at 2.5 pJ/bit across manufacturing lots, dice, voltages and temperature corners. The overall area is kept well below the 106 F2 area wall (F = minimum feature size).
Source Title: IEEE Solid-State Circuits Letters
URI: https://scholarbank.nus.edu.sg/handle/10635/191223
ISSN: 25739603
DOI: 10.1109/LSSC.2020.3025191
Rights: CC0 1.0 Universal
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