Please use this identifier to cite or link to this item: https://doi.org/10.1155/1998/57380
Title: Performance and wirability driven layout for row-based FPGAs
Authors: Nag, S 
Roy, K
Keywords: Electric network analysis
Electric wiring
Integrated circuit layout
Perturbation techniques
Routers
Post-layout timing analyzers
Row-based field programmable gate arrays (FPGA)
Field programmable gate arrays
Issue Date: 1998
Publisher: Hindawi Limited
Citation: Nag, S, Roy, K (1998). Performance and wirability driven layout for row-based FPGAs. VLSI Design 7 (4) : 353-364. ScholarBank@NUS Repository. https://doi.org/10.1155/1998/57380
Rights: Attribution 4.0 International
Abstract: In FPGAs the routing resources are fixed and their usage is constrained by the location of antifuses. In addition, the antifuses affect the layout performance significantly, depending on the technology. Hence, simplistic placement level assumptions turn out to be grossly inadequate in predicting the timing and wirability behavior of a layout. There is a need, therefore, for a layout technique which changes the layout at placement level based on accurate post-layout timing analysis and net wirability. In this paper we consider such a wirability and performance driven layout flow for row-based FPGAs. Timing information from a post-layout timing analyzer and wirability information from global and channel routers are used by an incremental placer to effectively perturb the placement. A large improvement (up to 29%) in timing has been obtained (compared to non-iterative FPGA layout) for a set of industrial designs and benchmark examples.
Source Title: VLSI Design
URI: https://scholarbank.nus.edu.sg/handle/10635/181142
ISSN: 1065514X
DOI: 10.1155/1998/57380
Rights: Attribution 4.0 International
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