Please use this identifier to cite or link to this item: https://doi.org/10.1145/3314148.3314353
Title: Precise Time-synchronization in the Data-Plane using Programmable Switching ASICs
Authors: PRAVEIN GOVINDAN KANNAN 
JOSHI RAJ 
CHAN MUN CHOON 
Keywords: Networks
Network services
Programmable networks
Issue Date: 3-Apr-2019
Publisher: Association for Computing Machinery, Inc
Citation: PRAVEIN GOVINDAN KANNAN, JOSHI RAJ, CHAN MUN CHOON (2019-04-03). Precise Time-synchronization in the Data-Plane using Programmable Switching ASICs. Proceedings of the 2019 ACM Symposium on SDN Research. ScholarBank@NUS Repository. https://doi.org/10.1145/3314148.3314353
Abstract: Current implementations of time synchronization protocols (e.g. PTP) in standard industry-grade switches handle the protocol stack in the slow-path (control-plane). With new use cases of in-network computing using programmable switching ASICs, global time-synchronization in the data-plane is very much necessary for supporting distributed applications. In this paper, we explore the possibility of using programmable switching ASICs to design and implement a time synchronization protocol, DPTP, with the core logic running in the data-plane. We perform comprehensive measurement studies on the variable delay characteristics in the switches and NICs under different traffic conditions. Based on the measurement insights, we design and implement DPTP on a Barefoot Tofino switch using the P4 programming language. Our evaluation on a multi-switch testbed shows that DPTP can achieve median and 99th percentile synchronization error of 19 ns and 47 ns between 2 switches, 4-hops apart, in the presence of clock drifts and under heavy network load.
Source Title: Proceedings of the 2019 ACM Symposium on SDN Research
URI: https://scholarbank.nus.edu.sg/handle/10635/168479
ISBN: 9781450367103
DOI: 10.1145/3314148.3314353
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