Precise Time-synchronization in the Data-Plane using Programmable Switching ASICs
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Abstract
Current implementations of time synchronization protocols (e.g. PTP) in standard industry-grade switches handle the protocol stack in the slow-path (control-plane). With new use cases of in-network computing using programmable switching ASICs, global time-synchronization in the data-plane is very much necessary for supporting distributed applications. In this paper, we explore the possibility of using programmable switching ASICs to design and implement a time synchronization protocol, DPTP, with the core logic running in the data-plane. We perform comprehensive measurement studies on the variable delay characteristics in the switches and NICs under different traffic conditions. Based on the measurement insights, we design and implement DPTP on a Barefoot Tofino switch using the P4 programming language. Our evaluation on a multi-switch testbed shows that DPTP can achieve median and 99th percentile synchronization error of 19 ns and 47 ns between 2 switches, 4-hops apart, in the presence of clock drifts and under heavy network load.
Keywords
Networks, Network services, Programmable networks
Source Title
Proceedings of the 2019 ACM Symposium on SDN Research
Publisher
Association for Computing Machinery, Inc
Series/Report No.
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Date
2019-04-03
DOI
10.1145/3314148.3314353
Type
Conference Paper