DESIGN, SIMULATION AND OPTIMIZATION OF HIGH Q RF SPIRAL INDUCTORS ON SILICON CHIPS

Abstract

In silicon-based radio-frequency integrated circuits, on-chip spiral inductors are widely used due to their low cost and ease of process integration. However, the lossy Si substrate makes the design of high Q passive components difficult. Although there have been many works done to find many methods to improve the Q factor, the optimization of the spiral inductors is a never end job, and there is a continually great incentive to design, optimize, and model spiral inductors fabricated on Si substrates. Our project firstly researches on the design and optimization of the spiral inductors with 6 µm Cu top layer based on the IME CMOS Cu interconnect technology. The effects of various structural and process parameters on the Q factor are explained in detail using the advanced electromagnetic simulator, HFSS, which shows the accurate simulation results and gives the guide for the on-chip inductors optimization. We finally find the optimal structure of n4w6s2t75th6 for the thick Cu inductors, which can improve the Q factor by 40% or so. The guide of optimizing 6 µm thick Cu spiral inductors is also given in detail in our project. At the meanwhile, we propose an equivalent circuit model, the advanced single-TT model using lumped RLC elements, to offer the physical insight of the planar inductors. Unlike the time-consuming 3-D simulator, the physical model can easily and quickly simulate the performance of the inductance L and the Q factor from the geometric structures of the inductors. The verification work has also been done to modify our scalable model with the measured results of various inductors.