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|Title:||Transport characteristics of Si nanowires in bulk silicon and SOI wafers||Authors:||Agarwal, A.
|Issue Date:||2006||Citation:||Agarwal, A., Singh, N., Liow, T.-Y., Kumar, R., Balasubramanian, N., Kwong, D.L. (2006). Transport characteristics of Si nanowires in bulk silicon and SOI wafers. NanoSingapore 2006: IEEE Conference on Emerging Technologies - Nanoelectronics - Proceedings 2006 : 67-70. ScholarBank@NUS Repository. https://doi.org/10.1109/NANOEL.2006.1609690||Abstract:||Silicon nanowires (SiNW) were fabricated on bulk Silicon and SOI wafers by means of conventional Si process technology. The nanowires were formed by stress-limited oxidation of Si beams pre-patterned on the wafer. Single or double vertically self-aligned wires were obtained depending on the bulk or SOI wafer used and also on the depth of silicon beam etched. The resulting nanowires exhibit triangular cross-section that can be converted to circular shape by annealing at high temperatures, exploiting the visco-elastic properties of SiO2 and Si. Electrical measurements on single nanowire show that the resistance scales with length demonstrating consistent cross-sectional dimension in wires of different length. The nanowires formed on SOI wafers were also characterized as channels in FET configuration, using substrate as gate electrode. This technique can be exploited for realizing several nano-electronics, NEMS and biosensor applications in bulk silicon or SOI wafers, all in a CMOS compatible manner. © 2006 IEEE.||Source Title:||NanoSingapore 2006: IEEE Conference on Emerging Technologies - Nanoelectronics - Proceedings||URI:||http://scholarbank.nus.edu.sg/handle/10635/130477||ISBN:||0780393589||DOI:||10.1109/NANOEL.2006.1609690|
|Appears in Collections:||Staff Publications|
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