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|Title:||Si nanowire CMOS transistors and circuits by top-down technology approach||Authors:||Balasubramanian, N.
|Issue Date:||2008||Citation:||Balasubramanian, N., Singh, N., Rustogi, S.C., Buddharaju, K.D., Fu, J., Hui, Z., Balakumar, S., Agarwal, A., Manhas, S.K., Lo, G.Q., Kwong, D.L. (2008). Si nanowire CMOS transistors and circuits by top-down technology approach. ECS Transactions 13 (1) : 201-211. ScholarBank@NUS Repository. https://doi.org/10.1149/1.2911501||Abstract:||For the end of the roadmap CMOS scaling, the non-classical device architecture, Gate All Around (GAA) FET with nanowire (NW) channel body offers the ultimate electro-static control and thus has the potential to push the gate length to few nanometers. The key challenge for NWs to be widely adopted in CMOS IC industry is that they have to be formed by large scale manufacturing methods and devoid of contamination issues. Top-down methods using lithography and etching suit CMOS applications in general and also provides a well-established CMOS based platform for creating devices for other applications. We have developed such a technology platform for Si NW fabrication with NW diameter down to 3 nm. This paper gives an overview of our technology approach, GAA Transistors, CMOS inverters, logic gates, ring oscillators, nanocrystal embedded SONOS memory devices and an introduction to high Ge content SiGe nanowires. © The Electrochemical Society.||Source Title:||ECS Transactions||URI:||http://scholarbank.nus.edu.sg/handle/10635/130092||ISBN:||9781566776264||ISSN:||19385862||DOI:||10.1149/1.2911501|
|Appears in Collections:||Staff Publications|
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