Rajesh Chandrasekhara Panicker

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Full Name

Variants

Panicker, R.C.

Main Affiliation

ELECTRICAL AND COMPUTER ENGINEERING
COLLEGE OF DESIGN AND ENGINEERING

Faculty

FAC OF ENGINEERING
COLLEGE OF DESIGN & ENG

eleraje@nus.edu.sg

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	Issue Date	Title	Author(s)
1	2007	A constrained genetic algorithm for efficient dimensionality reduction for pattern classification	Panicker, R.C. ; Puthusserypady, S.
2	Dec-2010	Adaptation in P300 braincomputer interfaces: A two-classifier cotraining approach	Panicker, R.C. ; Puthusserypady, S.; Sun, Y.
3	Jun-2011	An asynchronous P300 BCI with SSVEP-based control state detection	Panicker, R.C. ; Puthusserypady, S.; Sun, Y.
4	2010	Asynchronous P300 BCI: SSVEP-based control state detection	Panicker, R.C. ; Puthusserypady, S.; Pryana, A.P.; Sun, Y.
5	2012	Development of an FPGA-based real-time P300 speller	Khurana, K.; Gupta, P.; Panicker, R.C. ; Kumar, A.
6	2013	Enhancing VHDL learning through a light-weight integrated environment for development and automated checking	Kumar, A. ; Panicker, R.C. ; Kassim, A.