Pey Kin Leong

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Full Name

Pey Kin Leong

Variants

PEY, KIN-LEONG
PEY, KIN L.
LEONG, KIN
Pey, Kin Leong
PEY, KIN LEONG
Pey, K.L.

Main Affiliation

PHYSICS
ELECTRICAL AND COMPUTER ENGINEERING

Faculty

FAC OF SCIENCE
FAC OF ENGINEERING

Refined By:

Type: Patent

Author: CHAN, LAP

Results 1-5 of 5 (Search time: 0.002 seconds).

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	Issue Date	Title	Author(s)
1	20-May-2003	Incorporation of dielectric layer onto SThM tips for direct thermal analysis	HU, CHANG CHAUN; PEY, KIN LEONG ; CHONG, YUNG FU; KIN, CHIM WAI ; NEUZIL, PAVEL; CHAN, LAP
2	15-Feb-2011	Method for forming a shallow junction region using defect engineering and laser annealing	ONG, KUANG KIAN; YEONG, SAI HOOI; PEY, KIN LEONG ; CHAN, LAP; CHONG, YUNG FU
3	30-Jan-2001	Method to fabricate a double-polysilicon gate structure for a sub-quarter micron self-aligned-titanium silicide process	PEY, KIN-LEONG ; HO, CHAW SING; CHAN, LAP
4	4-Sep-2001	Method to reduce compressive stress in the silicon substrate during silicidation	CHA, RANDALL CHER LIANG; CHUA, CHEE TEE; PEY, KIN LEONG ; CHAN, LAP
5	25-Jul-2000	Ultra-low sheet resistance metal/poly-si gate for deep sub-micron CMOS application	LIM, CHONG WEE; PEY, KIN LEONG ; SIAH, SOH YUN; LIM, ENG HWA ; CHAN, LAP