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Pey Kin Leong

rp03121

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Full Name
Pey Kin Leong
Variants
PEY, KIN-LEONG
PEY, KIN L.
LEONG, KIN
Pey, Kin Leong
PEY, KIN LEONG
Pey, K.L.
 
Main Affiliation
 
Faculty
 

Publications

Refined By:
Type:  Patent
Author:  CHAN, LAP
Date Issued:  [2000 TO 2009]

Results 1-4 of 4 (Search time: 0.004 seconds).

Issue DateTitleAuthor(s)
120-May-2003Incorporation of dielectric layer onto SThM tips for direct thermal analysisHU, CHANG CHAUN; PEY, KIN LEONG ; CHONG, YUNG FU; KIN, CHIM WAI ; NEUZIL, PAVEL; CHAN, LAP
230-Jan-2001Method to fabricate a double-polysilicon gate structure for a sub-quarter micron self-aligned-titanium silicide processPEY, KIN-LEONG ; HO, CHAW SING; CHAN, LAP
34-Sep-2001Method to reduce compressive stress in the silicon substrate during silicidationCHA, RANDALL CHER LIANG; CHUA, CHEE TEE; PEY, KIN LEONG ; CHAN, LAP
425-Jul-2000Ultra-low sheet resistance metal/poly-si gate for deep sub-micron CMOS applicationLIM, CHONG WEE; PEY, KIN LEONG ; SIAH, SOH YUN; LIM, ENG HWA ; CHAN, LAP