Quantum mechanical modeling of gate capacitance and gate current in tunnel dielectric stack structures for nonvolatile memory application

Abstract

A self-consistent quantum mechanical (QM) numerical calculations, using an in-house developed charge quantization simulation program, were conducted to analyze the gate tunneling current and capacitance of metal-insulator- semiconductor (MIS) device with tunnel dielectric stack structures. The transmission probability through the dielectric stack structure was calculated by using a gate current density-gate voltage (Jg-Vg) simulation that uses a recursive method. It was shown that a physical model was used to fit with capacitance-voltage and Jg-Vg measurements on MIS devices with different single-layer dielectric and multilayered dielectric stack structures.