Please use this identifier to cite or link to this item:
|Title:||On the performance limit of impact-ionization transistors|
|Source:||Shen, C., Lin, J.-Q., Toh, E.-H., Chang, K.-F., Bait, P., Heng, C.-H., Samudra, G.S., Yeo, Y.-C. (2007). On the performance limit of impact-ionization transistors. Technical Digest - International Electron Devices Meeting, IEDM : 117-120. ScholarBank@NUS Repository. https://doi.org/10.1109/IEDM.2007.4418878|
|Abstract:||The trade-off between off-state leakage current and switching delay for Impact-Ionization MOS transistor (I-MOS) is pointed out and studied for the first time. This trade-off is unique for I-MOS devices, and is related to the self-amplifying carrier multiplication, the exact phenomenon used to be viewed as a merit. Monte-Carlo simulation is performed to study the random process of carrier multiplication in I-MOS, and the physical limit to the transistor switching delay is assessed. We found that at leakage constraints of 0.1,μA/μm, silicon I-MOS shows long intrinsic switch-on delay (>l0ps) and large random delay variance, hence does not show advantage in the delay/leakage trade-off compared to CMOS devices. © 2007 IEEE.|
|Source Title:||Technical Digest - International Electron Devices Meeting, IEDM|
|Appears in Collections:||Staff Publications|
Show full item record
Files in This Item:
There are no files associated with this item.
checked on Dec 6, 2017
WEB OF SCIENCETM
checked on Nov 19, 2017
checked on Dec 10, 2017
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.