On the performance limit of impact-ionization transistors

Please use this identifier to cite or link to this item: https://doi.org/10.1109/IEDM.2007.4418878

Title:	On the performance limit of impact-ionization transistors
Authors:	Shen, C. Lin, J.-Q. Toh, E.-H. Chang, K.-F. Bait, P. Heng, C.-H. Samudra, G.S. Yeo, Y.-C.
Issue Date:	2007
Citation:	Shen, C., Lin, J.-Q., Toh, E.-H., Chang, K.-F., Bait, P., Heng, C.-H., Samudra, G.S., Yeo, Y.-C. (2007). On the performance limit of impact-ionization transistors. Technical Digest - International Electron Devices Meeting, IEDM : 117-120. ScholarBank@NUS Repository. https://doi.org/10.1109/IEDM.2007.4418878
Abstract:	The trade-off between off-state leakage current and switching delay for Impact-Ionization MOS transistor (I-MOS) is pointed out and studied for the first time. This trade-off is unique for I-MOS devices, and is related to the self-amplifying carrier multiplication, the exact phenomenon used to be viewed as a merit. Monte-Carlo simulation is performed to study the random process of carrier multiplication in I-MOS, and the physical limit to the transistor switching delay is assessed. We found that at leakage constraints of 0.1,μA/μm, silicon I-MOS shows long intrinsic switch-on delay (>l0ps) and large random delay variance, hence does not show advantage in the delay/leakage trade-off compared to CMOS devices. © 2007 IEEE.
Source Title:	Technical Digest - International Electron Devices Meeting, IEDM
URI:	http://scholarbank.nus.edu.sg/handle/10635/71238
ISSN:	01631918
DOI:	10.1109/IEDM.2007.4418878
Appears in Collections:	Staff Publications

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