On the performance limit of impact-ionization transistors

Abstract

The trade-off between off-state leakage current and switching delay for Impact-Ionization MOS transistor (I-MOS) is pointed out and studied for the first time. This trade-off is unique for I-MOS devices, and is related to the self-amplifying carrier multiplication, the exact phenomenon used to be viewed as a merit. Monte-Carlo simulation is performed to study the random process of carrier multiplication in I-MOS, and the physical limit to the transistor switching delay is assessed. We found that at leakage constraints of 0.1,μA/μm, silicon I-MOS shows long intrinsic switch-on delay (>l0ps) and large random delay variance, hence does not show advantage in the delay/leakage trade-off compared to CMOS devices. © 2007 IEEE.