POWER-AWARE TECHNOLOGY MAPPING AND ROUTING FOR DUAL-VT FPGAS

Abstract

In this thesis, we present a technology mapping and clustering scheme, as well as a novel interconnect routing architecture, for modern FPGAs with programmable dual-V_T fabrics. The use of Reverse Back Bias (RBB) in circuit design is recognized today as a feasible strategy for mitigating leakage power, a critical issue as process technologies shrink relentlessly towards sub-nanometre proportions. FPGAs with the ability to adjust fabric V_T at configuration time offers the ability to reduce leakage power reduction with minimal or no sacrifice to circuit speed.

Today, Altera¿s Stratix-III/IV line of FPGAs already demonstrate the feasibility of a similar architecture, but with dual-V_T optimization limited to post-P&R. We explore the limitations of such an approach. We also discuss why a dual-V_T solution is superior to a dual-V_DD one, an architecture adopted by some of the existing works in academia. Together, these form the basis for the contributions presented in this thesis.

The first work presented is RBBMap, a power-aware, dual-V_T technology mapping tool, and RBBPack, a dual-V_T logic clustering tool. Using an existing baseline tool Emap, the combined use of RBBMap and RBBPack yields an average of 70.95% and 28.30% savings in logic block leakage and total power respectively. The second work explores a completely new domain: a programmable, dual-V_T switch box routing architecture. This work holds promise in mitigating leakage power in the interconnect - the largest constituent component of the FPGA, yielding an average of 53.69% and 28.23% savings in leakage power savings on the routing network and in total power respectively.