Please use this identifier to cite or link to this item:
https://scholarbank.nus.edu.sg/handle/10635/32500
DC Field | Value | |
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dc.title | POWER-AWARE TECHNOLOGY MAPPING AND ROUTING FOR DUAL-VT FPGAS | |
dc.contributor.author | LOKE WEI TING | |
dc.date.accessioned | 2012-04-30T18:01:47Z | |
dc.date.available | 2012-04-30T18:01:47Z | |
dc.date.issued | 2012-01-20 | |
dc.identifier.citation | LOKE WEI TING (2012-01-20). POWER-AWARE TECHNOLOGY MAPPING AND ROUTING FOR DUAL-VT FPGAS. ScholarBank@NUS Repository. | |
dc.identifier.uri | http://scholarbank.nus.edu.sg/handle/10635/32500 | |
dc.description.abstract | In this thesis, we present a technology mapping and clustering scheme, as well as a novel interconnect routing architecture, for modern FPGAs with programmable dual-V<sub>T</sub> fabrics. The use of Reverse Back Bias (RBB) in circuit design is recognized today as a feasible strategy for mitigating leakage power, a critical issue as process technologies shrink relentlessly towards sub-nanometre proportions. FPGAs with the ability to adjust fabric V<sub>T</sub> at configuration time offers the ability to reduce leakage power reduction with minimal or no sacrifice to circuit speed. Today, Altera¿s Stratix-III/IV line of FPGAs already demonstrate the feasibility of a similar architecture, but with dual-V<sub>T</sub> optimization limited to post-P&R. We explore the limitations of such an approach. We also discuss why a dual-V<sub>T</sub> solution is superior to a dual-V<sub>DD</sub> one, an architecture adopted by some of the existing works in academia. Together, these form the basis for the contributions presented in this thesis. The first work presented is RBBMap, a power-aware, dual-V<sub>T</sub> technology mapping tool, and RBBPack, a dual-V<sub>T</sub> logic clustering tool. Using an existing baseline tool Emap, the combined use of RBBMap and RBBPack yields an average of 70.95% and 28.30% savings in logic block leakage and total power respectively. The second work explores a completely new domain: a programmable, dual-V<sub>T</sub> switch box routing architecture. This work holds promise in mitigating leakage power in the interconnect - the largest constituent component of the FPGA, yielding an average of 53.69% and 28.23% savings in leakage power savings on the routing network and in total power respectively. | |
dc.language.iso | en | |
dc.subject | Technology Mapping, Routing, Reverse Back Bias, Dual VT, FPGA, EDA | |
dc.type | Thesis | |
dc.contributor.department | ELECTRICAL & COMPUTER ENGINEERING | |
dc.contributor.supervisor | HA YAJUN | |
dc.description.degree | Master's | |
dc.description.degreeconferred | MASTER OF ENGINEERING | |
dc.identifier.isiut | NOT_IN_WOS | |
Appears in Collections: | Master's Theses (Open) |
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File | Description | Size | Format | Access Settings | Version | |
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rbbthesis_final.pdf | 2.7 MB | Adobe PDF | OPEN | None | View/Download |
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